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ics951901 integrated circuit systems, inc. 0670b?07/15/04 programmable frequency generator & integrated buffers for pentium iii processor block diagram recommended application: single chip clock solution for ia platform. output features: 3 - cpu @ 2.5v 13 - sdram @ 3.3v 6 - pci @3.3v, 2 - agp @ 3.3v 1 - 48mhz, @3.3v fixed. 1 - 24/48mhz, @3.3v selectable by i 2 c (default is 24mhz) 2 - ref @3.3v, 14.318mhz. features: programmable ouput frequency. programmable ouput rise/fall time. programmable sdram and cpu skew. spread spectrum for emi control typically by 7db to 8db, with programmable spread percentage. watchdog timer technology to reset system if over-clocking causes malfunction. uses external 14.318mhz crystal. fs pins for frequency select skew specifications: cpu - cpu: < 175ps sdram - sdram < 250ps (except sdram12) pci - pci: < 500ps cpu (early) - pci: 1-4ns (typ. 2ns) functionality pin configuration 48-pin 300mil ssop * these inputs have a 120k pull down to gnd. 1 these are double strength. pll2 pll1 spread spectrum 48mhz 24_48mhz cpuclk (2:0) sdram (12:0) pciclk (4:0) agp (1:0) pciclk_f 2 5 13 3 2 x1 x2 xtal osc cpu divder sdram divder pci divder stop stop stop s data sclk fs(3:0) pd# pci_stop# cpu_stop# sdram_stop# mode agp_sel control logic config. reg. / 2 ref(1:0) agp divder vdda (agpsel)ref0 *(fs3)ref1 gnd x1 x2 vddpci *(fs1)pciclk_f *(fs2)pciclk0 pciclk1 pciclk2 pciclk3 pciclk4 gnd vddagp agpclk0 agpclk1 gnd gnd *(fs0)48mhz *(mode)24_48mhz vdd48 s data sclk 1 1 * vddl cpuclk0 cpuclk1 cpuclk2 gnd vddsdr sdram0 sdram1 sdram2 gnd sdram3 sdram4 sdram5 vddsdr sdram6 sdram7 gnd sdram8/pd# sdram9/sdram_stop# gnd sdram10/pci_stop# sdram11/cpu_stop# sdram12 vddsdr ics9519 01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 fs3fs2fs1fs0cpu sdram pci agp1 agp0 bit7 bit6 bit5 bit4 mhz mhz mhz sel=1 sel=0 0 0 0 0 0 66.67 66.67 33.33 66.67 64 0 0 0 0 1 66.67 100.00 33.33 66.67 64 0 0 0 1 0 66.67 133.34 33.33 66.67 64 0 0 0 1 1 75.00 75.00 37.50 75.00 64 0 0 1 0 0 83.31 83.31 33.32 66.64 64 0 0 1 0 1 90.00 90.00 30.00 60.00 64 0 0 1 1 0 95.00 95.00 31.67 63.33 64 0 0 1 1 1 100.00 66.67 33.33 66.67 64 0 1 0 0 0 100.00 100.00 33.33 66.67 64 0 1 0 0 1 100.00 133.34 33.33 66.67 64 0 1 0 1 0 105.00 105.00 35.00 70.00 64 0 1 0 1 1 112.00 112.00 33.60 67.20 64 0 1 1 0 0 117.99 117.99 35.40 70.80 64 0 1 1 0 1 124.09 124.09 31.02 62.05 64 0 1 1 1 0 133.34 100.00 33.33 66.67 64 01111 133.34 133.34 33.33 66.67 64 bit2
2 ics951901 0670b?07/15/04 general description pin configuration the ics951901 is a single chip clock solution for desktop designs using 630s chipsets. it provides all necessary clock signals for such a system. the ics951901 belongs to ics new generation of programmable system clock generators. it employs serial programming i 2 c interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. this device also has ics propriety 'watchdog timer' technology which will reset the frequency to a safe setting if the system becomes unstable from over clocking. power groups analog vdda = x1, x2, core, pll vdd48 = 48mhz, 24mhz, fixed pll digital vddpci = pciclk_f, pciclk vddsdr = sdram vddagp=agp, ref e d o m 1 2 n i p 7 2 n i p8 2 n i p0 3 n i p1 3 n i p 01 1 m a r d s0 1 m a r d s9 m a r d s8 m a r d s 1# p o t s _ u p c# p o t s _ i c p# p o t s _ m a r d s# d p mode pin power management control input pin number pin name type description 1, 7, 15, 22, 25, 35, 43 vdd pwr 3.3v power supply for sdram output buffers, pci output buffers, reference output buffers and 48mhz output agpsel in agp fr equency select pin. ref0 out 14.318 mhz reference clock. fs3 in frequency select pin. ref1 out 14.318 mhz reference clock. 4, 14, 18, 19, 29, 32, 39, 44 gnd pwr ground pin for 3v outputs. 5 x1 in crystal input,nominally 14.318mhz. 6 x2 out crystal output, nominally 14.318mhz. fs1 in frequency select pin. pciclk_f out pci clock output, not affected by pci_stop# fs2 in frequency select pin. pciclk0 out pci clock output. 13, 12, 11, 10 pciclk (4:1) out pci clock outputs. 17, 16, agp (1:0) out agp outputs defined as 2x pci. these may not be stopped. fs0 in frequency select pin. 48mhz out 48mhz output clock mode in pin 27, 28, 30, & 31 function select pin 0=desktop 1=mobile mode 24_48mhz out clock output for super i/o/usb default is 24mhz 23 sdata i/o data pin for i 2 c circuitry 5v tolerant 24 sclk in clock pin of i 2 c circuitry 5v tolerant cpu_stop# in stops all pciclks besides the pciclk_f clocks at logic 0 level, when input is low and mode pin is in mobile mode sdram11 out sdram clock output pci_stop# in stops all cpuclks clocks at logic 0 level, when input is low and mode pin is in mobile mode sdram10 out sdram clock output sdram9 out sdram clock output sdram_stop# in stops all sdram clocks at logic 0 level, when input is low and mode pin is in mobile mode pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 3ms sdram8 out sdram clock output 26 33, 34, 36, 37, 38, 40, 41, 42 sdram (12, 7:0) out sdram clock outputs 45, 46, 47 cpuclk (2:0) out cpu clock outputs. 48 vddl pwr power pin for the cpuclks. 2.5v 31 20 2 8 9 21 3 30 27 28
3 ics951901 0670b?07/15/04 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note: pwd = power-up default note1: default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. i 2 c is a trademark of philips corporation fs3 fs2 fs1 fs0 cpu sdram pci agp1 agp0 spread % pwd bit2 bit7 bit6 bit5 bit4 mhz mhz mhz sel=1 sel=0 0000066.6766.6733.3366.6764 0.35% center spread 0000166.67100.0033.3366.6764 0.35% center spread 0001066.67133.3433.3366.6764 0.35% center spread 0001175.0075.0037.5075.0064 0.35% center spread 0010083.3183.3133.3266.6464 0.35% center spread 0010190.0090.0030.0060.0064 0.35% center spread 0011095.0095.0031.6763.3364 0.35% center spread 00111 100.00 66.67 33.33 66.67 64 0.35% center spread 01000 100.00 100.00 33.33 66.67 64 0.35% center spread 01001100.00133.3433.3366.6764 0.35% center spread 01010105.00105.0035.0070.0064 0.35% center spread 01011112.00112.0033.6067.2064 0.35% center spread 01100117.99117.9935.4070.8064 0.35% center spread 01101124.09124.0931.0262.0564 0.35% center spread bit 201110133.34100.0033.3366.6764 0.35% center spread 00000 bit 7:401111 133.34 133.34 33.33 66.67 64 0.35% center spread note1 10000 75.00 100.00 37.50 75.00 64 0.35% center spread 1000175.00112.5032.1464.2964 0.35% center spread 1001075.00150.0032.1464.2964 0.35% center spread 1001183.31111.0733.3266.6464 0.35% center spread 1010083.32166.6531.2562.4964 0.35% center spread 1010190.0060.0030.0060.0064 0.35% center spread 1011090.00120.0030.0060.0064 0.35% center spread 10111 95.00 63.33 31.67 63.33 64 0.35% center spread 11000 95.00 126.66 31.67 63.33 64 0.35% center spread 11001105.0070.0035.0070.0064 0.35% center spread 11010105.00140.0035.0070.0064 0.35% center spread 11011112.0084.0033.6067.2064 0.35% center spread 11100117.9988.4935.4070.8064 0.35% center spread 11101124.0993.0731.0262.0564 0.35% center spread 11110129.9997.4932.5064.9964 0.35% center spread 11111140.00105.0035.0070.0064 0.35% center s p read bit 3 0 - frequency is selected by hardware select, latched inputs 0 1 - frequency is selected by bit, 2 7:4 bit 1 0 - normal 1 1 - spread spectrum enabled bit 0 0 - running 0 1 - tristate all outputs bit description
4 ics951901 0670b?07/15/04 byte 1: cpu, active/inactive register (1= enable, 0 = disable) byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b3 11 4 k l c i c p 4 t i b2 11 3 k l c i c p 3 t i b1 11 2 k l c i c p 2 t i b0 11 1 k l c i c p 1 t i b91 0 k l c i c p 0 t i b81 f _ k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b1 21 z h m 8 4 _ 4 2 5 t i b0 21 z h m 8 4 4 t i b6 21 2 1 m a r d s 3 t i b7 21 1 1 m a r d s 2 t i b8 21 0 1 m a r d s 1 t i b0 31 9 m a r d s 0 t i b1 31 8 m a r d s byte 4: sdram , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x ) k c a b d a e r ( 3 s f 6 t i b-x ) k c a b d a e r ( 2 s f 5 t i b-x ) k c a b d a e r ( 1 s f 4 t i b-x ) k c a b d a e r ( 0 s f 3 t i b310 f e r 2 t i b211 f e r 1 t i b7 11 1 k l c p g a 0 t i b6 11 0 k l c p g a byte 5: agp, active/inactive register (1= enable, 0 = disable) byte 3: sdram, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b3 31 7 m a r d s 6 t i b4 31 6 m a r d s 5 t i b6 31 5 m a r d s 4 t i b7 31 4 m a r d s 3 t i b8 31 3 m a r d s 2 t i b0 41 2 m a r d s 1 t i b1 41 1 m a r d s 0 t i b2 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 8 4 _ 4 2 l e s ) z h m 8 4 : 0 , z h m 4 2 : 1 ( 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b7 41 0 k l c u p c 2 t i b6 41 1 k l c u p c 1 t i b5 41 2 k l c u p c 0 t i b-1 d e v r e s e r
5 ics951901 0670b?07/15/04 byte 6: control , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-0 d e v r e s e r 1 t i b-0 d e v r e s e r 0 t i b-1 d e v r e s e r byte 7: vendor id register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b3 , 20 x 2 = 1 , x 1 = 0 h t g n e r t s f e r 6 t i b5 40 l o r t n o c - p o t s - 2 k l c u p c , 2 k l c u p c l o r t n o c l l i w # p o t s _ u p c = 0 w o l s i # p o t s _ u p c f i n e v e g n i n n u r e e r f s i 2 k l c u p c = 1 5 t i b-x ) k c a b d a e r ( l e s p g a 4 t i b-x ) k c a b d a e r ( e d o m 3 t i b-x ) k c a b d a e r ( # p o t s _ u p c 2 t i b-x ) k c a b d a e r ( # p o t s _ i c p 1 t i b-x ) k c a b d a e r ( # p o t s _ m a r d s 0 t i b-0 e l g g o t d e e p s p g a , g n i t t e s t u p n i h c t a l y b d e n i m r e t e d e b l l i w ) 2 n i p ( l e s p g a = 0 g n i t t e s t u p n i h c t a l f o e t i s o p p o e b l l i w l e s p g a = 1 byte 8: byte count and read back register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 d e v r e s e r 6 t i b-0 d e v r e s e r 5 t i b-0 d e v r e s e r 4 t i b-0 d e v r e s e r 3 t i b-0 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-0 d e v r e s e r 0 t i b-0 d e v r e s e r note: fs values in bit [0:4] will correspond to byte 0 fs values. default safe frequency is same as 00000 entry in byte0. byte 10: vco control selection bit & watchdog timer control register t i bd w pn o i t p i r c s e d 7 t i b0 q e r f 2 1 & 1 1 b = 1 / q e r f 0 b / w h = 0 6 t i b0 e l b a n e = 1 / e l b a s i d = 0 e l b a n e d w 5 t i b0 m r a l a = 1 / l a m r o n = 0 s u t a t s d w 4 t i b0 2 t i b 0 e t y b , y c n e u q e r f e f a s d w 3 t i b0 3 s f , y c n e u q e r f e f a s d w 2 t i b0 2 s f , y c n e u q e r f e f a s d w 1 t i b0 1 s f , y c n e u q e r f e f a s d w 0 t i b0 0 s f , y c n e u q e r f e f a s d w byte 9: watchdog timer count register t i bd w pn o i t p i r c s e d 7 t i b0 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t s m 1 r o s m 0 9 2 o t d n o p s e r r o c s t i b 8 e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t e h t t e s e r d n a e d o m m r a l a o t s e o g t i t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f 6 . 4 = s m 0 9 2 x 6 1 s i p u r e w o p t a . s d n o c e s 6 t i b0 5 t i b0 4 t i b1 3 t i b0 2 t i b0 1 t i b0 0 t i b0
6 ics951901 0670b?07/15/04 notes: 1. pwd = power on default byte 11: vco frequency control register note: the decimal representation of these 7 bits (byte 11 [6:0]) + 2 is equal to the ref divider value . t i bd w pn o i t p i r c s e d 7 t i bx 0 t i b r e d i v i d o c v 6 t i bx 6 t i b r e d i v i d f e r 5 t i bx 5 t i b r e d i v i d f e r 4 t i bx 4 t i b r e d i v i d f e r 3 t i bx 3 t i b r e d i v i d f e r 2 t i bx 2 t i b r e d i v i d f e r 1 t i bx 1 t i b r e d i v i d f e r 0 t i bx 0 t i b r e d i v i d f e r byte 12: vco frequency control register note: the decimal representation of these 9 bits (byte 12 bit [7:0] & byte 11 bit [7] ) + 8 is equal to the vco divider value. for example if vco divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7. t i bd w pn o i t p i r c s e d 7 t i bx 8 t i b r e d i v i d o c v 6 t i bx 7 t i b r e d i v i d o c v 5 t i bx 6 t i b r e d i v i d o c v 4 t i bx 5 t i b r e d i v i d o c v 3 t i bx 4 t i b r e d i v i d o c v 2 t i bx 3 t i b r e d i v i d o c v 1 t i bx 2 t i b r e d i v i d o c v 0 t i bx 1 t i b r e d i v i d o c v byte 13: spread sectrum control register byte 14: spread sectrum control register note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b m u r t c e p s d a e r p s 6 t i bx 6 t i b m u r t c e p s d a e r p s 5 t i bx 5 t i b m u r t c e p s d a e r p s 4 t i bx 4 t i b m u r t c e p s d a e r p s 3 t i bx 3 t i b m u r t c e p s d a e r p s 2 t i bx 2 t i b m u r t c e p s d a e r p s 1 t i bx 1 t i b m u r t c e p s d a e r p s 0 t i bx 0 t i b m u r t c e p s d a e r p s t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx 2 1 t i b m u r t c e p s d a e r p s 3 t i bx 1 1 t i b m u r t c e p s d a e r p s 2 t i bx 0 1 t i b m u r t c e p s d a e r p s 1 t i bx 9 i b m u r t c e p s d a e r p s 0 t i bx 8 t i b m u r t c e p s d a e r p s note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. byte 15: output skew control byte 16: output skew control t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c w e k s 2 1 m a r d s 6 t i b0 5 t i b0 l o r t n o c w e k s ) 0 : 1 1 ( m a r d s 4 t i b1 3 t i b1 l o r t n o c w e k s 2 k l c u p c 2 t i b1 1 t i b1 l o r t n o c w e k s ) 0 : 1 ( k l c u p c 0 t i b0 t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r
7 ics951901 0670b?07/15/04 byte 17: output rise/fall time select register byte 18: output rise/fall time select register t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c e t a r w e l s ) 0 : 3 ( i c p 6 t i b0 5 t i b1 l o r t n o c e t a r w e l s f _ i c p 4 t i b0 3 t i b1 l o r t n o c e t a r w e l s 2 k l c u p c 2 t i b0 1 t i b 0l o r t n o c e t a r w e l s 1 k l c u p c 0 t i b t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c e t a r w e l s : 2 1 m a r d s 6 t i b0 5 t i b1 l o r t n o c e t a r w e l s : 1 k l c p g a 4 t i b0 3 t i b1 l o r t n o c e t a r w e l s : 0 k l c p g a 2 t i b0 1 t i b1 l o r t n o c e t a r w e l s : 4 k l c i c p 0 t i b0 byte 19: output rise/fall time select register byte 20: output rise/fall time select register t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c e t a r w e l s : z h m 8 4 6 t i b0 5 t i b1 l o r t n o c e t a r w e l s : z h m 8 4 _ 4 2 4 t i b0 3 t i b1 l o r t n o c e t a r w e l s : 1 f e r 2 t i b0 l o r t n o c e t a r w e l s : 0 f e r 1 t i b1 l o r t n o c e t a r w e l s : ) 0 : 1 1 ( m a r d s 0 t i b0 t i bd w pn o i t p i r c s e d 7 t i b0 d e v r e s e r 6 t i b0 d e v r e s e r 5 t i b0 d e v r e s e r 4 t i b0 d e v r e s e r 3 t i b0 d e v r e s e r 2 t i b0 d e v r e s e r 1 t i b 0l o r t n o c e t a r w e l s 0 k l c u p c 0 t i b vco programming constrains vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 useful formula vco frequency = 14.31818 x vco/ref divider value phase detector stabiliy = 14.038 x (vco divider value) -0.5 to program the vco frequency for over-clocking. 0. before trying to program our clock manually, consider using ics provided software utilities for easy programming. 1. select the frequency you want to over-clock from with the desire gear ratio (i.e. cpu:sdram:3v66:pci ratio) by writing to byte 0, or using initial hardware power up frequency. 2. write 0001, 1001 (19 h ) to byte 8 for readback of 21 bytes (byte 0-20). 3. read back byte 11-20 and copy values in these registers. 4. re-initialize the write sequence. 5. write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired vco & ref divider values. 6. write to byte 13 to 20 with the values you copy from step 3. this maintains the output spread, skew and slew rate. 7. the above procedure is only needed when changing the vco for the 1st pass. if vco frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
8 ics951901 0670b?07/15/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters ta = 0 - 70c; supply volt age vdd = 3.3 v +/-5%vddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v supply current i dd c l =30 pf, cpu @ 66, 100 mhz 390 400 ma power down pd 300 600 ma input frequency fi v dd = 3.3 v; 12 14.32 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf transition time t trans to 1st crossing of target freq. 3 settling time t s from 1st crossing to 1% target freq. clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew t cpu-pci cpuv t = 1.5 v pci v t =1.25v 1 1.9 4 ns skew t cpu-sdram cpuv t = 1.5 v sdram v t =1.25 -500 -300 0 ps 1 guaranteed b y desi g n, not 100% tested in p roduction.
9 ics951901 0670b?07/15/04 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; vddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp2b v o = v dd *(0.5) 10 20 output impedance 1 r dsn2b v o = v dd *(0.5) 10 20 output high voltage v oh2b i oh = -12.0 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v output high current i oh2b v oh = 1.7 v -19 ma output low current i ol2b v ol = 0.7 v 19 ma rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.2 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 46.9 55 % skew window 0:1 t sk2b v t = 1.25 v 43 175 ps skew window 0:2 t sk2b v t = 1.25 v 142 375 ps jitter, cycle-to-cycle 1 t jcyc-cyc v t = 1.25 v, cpu=66 mhz 177 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 24-48mhz t a = 0 - 70c; v dd = 3.3 v +/-5%;vddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp5b 1 v o = v d d *(0.5) 20 60 output impedance r dsn5b 1 v o = v d d *(0.5) 20 60 output high voltage v oh15 i oh = -14 ma 2.4 v output low voltage v ol5 i ol = 6.0 ma 0.4 v output high current i oh5 v oh = 2.0 v -20 ma output low current i ol5 v ol = 0.8 v 10 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.4 1.45 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.4 1.5 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52.5 55 % jitter t cycle to cycle v t = 1.5 v 210 500 ps 1 guaranteed by design, not 100% tested in production.
10 ics951901 0670b?07/15/04 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; vddl = 2.5 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp1b 1 v o = v dd *(0.5) 12 55 output impedance r dsn1b 1 v o = v dd *(0.5) 12 55 output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v -29 ma output low current i ol1 v ol @ min = 1.95 v 29 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2.3 2.5 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2.3 2.5 ns dut y c y cle 1 d t1 v t = 1.5 v 45 51.2 55 % skew window 1 t sk1 v t = 1.5 v 108 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 353 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%;vddl = 2.5 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp3b 1 v o = v d d *(0.5) 10 24 output impedance r dsn3b 1 v o = v d d *(0.5) 10 24 output high voltage v oh3 i oh = -18 ma 2.4 v output low voltage v ol3 i ol = 9.4 ma 0.4 v output high current i oh3 v oh = 2.0 v -46 ma output low current i ol3 v ol = 0.8v ma rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.8 1.6 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.8 1.6 ns duty cycle 1 d t3 v t = 1.5 v 45 48.5 55 % skew window 1(0:11) t sk3 v t = 1.5 v 192 250 ps skew window 1( 0:12) t sk3 v t = 1.5 v 290 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc3 v t = 1.5 v, cpu=66,100,133 mhz 173 250 ps 1 guaranteed by design, not 100% tested in production.
11 ics951901 0670b?07/15/04 electrical characteristics - agp t a = 0 - 70c; v dd =3.3v +/-5%; c l = 20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o =v d d *(0.5) 12 55 output impedance r dsn4b 1 v o =v d d *(0.5) 12 55 output high voltage v oh4b i oh = -18 ma 2 v output low voltage v ol4b i ol = 18 ma 0.4 v output high current i oh4b v oh = 2.0 v -19 ma output low current i ol4b v ol = 0.8 v 19 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.4 v 0.5 1.5 2 ns fall time 1 t f4b v oh = 2.4 v, v ol = 0.4 v 0.5 1.6 2 ns dut y c y cle 1 d t4b v t = 1.5 v 45 52.3 55 % skew window1 tsk 1 v t = 1.5 v 55.5 175 ps jitter cyc-cyc tjcyc-cyc 1 v t = 1.5 v 239 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref ta = 0 - 70c; vdd = 3.3 v +/-5%;vddl = 2.5 v +/-5%; cl = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, voh = 2.4 v 1.8 4 ns fall time 1 t f5 v oh = 2.4 v, vol = 0.4 v 1.9 4 ns duty cycle 1 d t5 v t = 50% 45 54.5 55 % 1 guaranteed b y desi g n, not 100% tested in production.
12 ics951901 0670b?07/15/04 general i 2 c serial interface information for the ics951901 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending byte 0 through byte 28 (see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends byte 0 through byte 6 (default) ? ics clock sends byte 0 through byte x (if x (h) was written to byte 6). ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit *see notes on the following page . controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 18 ack byte 19 ack byte 20 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 1a h has been written to b6 byte18 ack if 1b h has been written to b6 byte 19 ack if 1c h has been written to b6 byte 20 ack stop bit how to read:
13 ics951901 0670b?07/15/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to readback is defined by writing to byte 8. 2. when writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8 bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. notes: brief i 2 c registers description for ics951901 programmable system frequency generator register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-6 active / inactive output control registers/latch inputs read back. see individual byte description vendor id & revision id registers 7 byte 11 bit[7:4] is ics vendor id - 1001. other bits in this register designate device revision id of this part. see individual byte description byte count read back register 8 writing to this register will configure byte count and how many byte will be read back. do not write 00 h to this byte. 08 h watchdog timer count register 9 writing to this register will configure the number of seconds for the watchdog timer to reset. 10 h watchdog control registers 10 bit [6:0] watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 10 bit [7] this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 vco frequency control registers 11-12 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 13-14 these registers control the spread percentage amount. depended on hardware/byte 0 configuration group skews control registers 15-16 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 17-20 these registers will control the output rise and fall time. see individual byte description
14 ics951901 0670b?07/15/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics951901 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power- on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
15 ics951901 0670b?07/15/04 cpu_stop# timing diagram cpu_stop# is an asychronous input to the clock synthesizer. it is used to turn off the cpu clocks for low power operation. cpu_stop# is synchronized by the ics94209 . the minimum that the cpu clock is enabled (cpu_stop# high pulse) is 100 cpu clocks. all other clocks will continue to run while the cpu clocks are disabled. the cpu clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpu clock on latency is less than 4 cpu clocks and cpu clock off latency is less than 4 cpu clocks. notes: 1. all timing is referenced to the internal cpu clock. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpu clocks inside the ics94209. 3. all other clocks continue to run undisturbed. (including sdram outputs).
16 ics951901 0670b?07/15/04 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics94209 . it is used to turn off the pciclk clocks for low power operation. pci_stop# is synchronized by the ics94209 internally. the minimum that the pciclk clocks are enabled (pci_stop# high pulse) is at least 10 pciclk clocks. pciclk clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics94209 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics94209. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state.
17 ics951901 0670b?07/15/04 sdram_stop# timing diagram sdram_stop# is an asychronous input to the clock synthesizer. it is used to stop sdram clocks for low power operation. sdram_stop# is synchronized to complete it's current cycle, by the ics94209 . all other clocks will continue to run while the sdram clocks are disabled. the sdram clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. notes: 1. all timing is referenced to the internal cpu clock. 2. sdram is an asynchronous input and metastable conditions may exist. this signal is synchronized to the sdram clocks inside the ics94209. 3. all other clocks continue to run undisturbed.
18 ics951901 0670b?07/15/04 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics94209 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz.
19 ics951901 0670b?07/15/04 ordering information ics951901 y flf-t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) example: designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxxxx y f lf- t

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